1. Field of the Invention
The present invention relates to a semiconductor device having a PDP (Plasma Display Panel) address driver IC.
2. Description of Related Art
A PDP driver IC (Integrated Circuit) includes a scan driver IC for driving scanning lines and an address driver IC for driving data lines. The address driver IC is provided with a low-voltage logic part and a high-voltage output part. FIG. 1 is a diagram showing a configuration example of an output cell of the address driver IC. A single output cell has the high-voltage output part 10 and the low-voltage logic part 11, and many output cells are integrated on a chip of the address driver IC.
The low-voltage logic part 11 includes a CMOS circuit. The low-voltage logic part 11 is connected to power supply potential VDD1 and ground (GND) potential VSS1. The low-voltage logic part 11 receives image data from a former-stage circuit and generates a drive signal to output it to the high-voltage output part 10. The high-voltage output part 10 includes a high-voltage N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (hereinafter referred to as an HVNch) and a high-voltage P-channel MOSFET (hereinafter referred to as an HVPch). The high-voltage output part 10 is connected to power supply potential VDD2 and GND potential VSS2. The high-voltage output part 10 outputs a PDP drive voltage based on the drive signal received from the low-voltage logic part 11.
The high-voltage output part 10 and the low-voltage logic part 11 are different in the power supply potential used. The VDD1 used in the low-voltage logic part 11 is generally on the order of several volts such as 3.3 V to 5.0 V. Whereas, the VDD2 used in the high-voltage output part 10 is tens of volts to hundreds of volts. The VSS1 of the low-voltage logic part 11 and the VSS2 of the high-voltage output part 10 are connected within the chip through a resistor R.
FIG. 2 is a diagram showing a configuration example of the address driver IC of a TCP (Tape Carrier Package). The address driver IC is provided with a plurality of output cells on a single chip. In FIG. 2, the high-voltage output parts 10-1 to 10-3 of the plurality of output cells are illustrated. In practice, the address driver IC 200 is provided with a lot more (e.g. 192) output cells on a single chip. Each of the high-voltage output parts 10-1 to 10-3 is connected to a system power supply through a VDD2 terminal to receive the VDD2 and also is connected to a system GND through a VSS2 terminal to receive the VSS2.
In this manner, lots of high-voltage output parts 10 are connected to the power supply line of the address driver IC. Therefore, when a switching operation is carried out simultaneously in a plurality of high-voltage output parts 10, a large current flows from the VSS2 terminal to the system GND. At this time, rising or ringing of the VSS2 potential is caused by characteristic impedance mismatch on wiring between the VSS2 terminal and the system GND, which causes fluctuation in the VSS2 potential. Such fluctuation in the VSS2 potential leads to logic malfunction of the high-voltage output part 10. Moreover, the fluctuation in the VSS2 potential also affects the VSS1 potential connected to the VSS2 through the resistor, which leads to malfunction of the low-voltage logic part 11.
These problems described above can be solved by reducing a drive current of the PDP panel or reducing impedance on a wiring (hereinafter referred to as wiring impedance). However, the drive current of the PDP panel depends on characteristics of the PDP panel and it is thus difficult to change the drive current. Therefore, techniques for reducing the wiring impedance have been considered. A related technique is as follows.
Japanese Patent Publication JP-2008-203376A (hereinafter referred to as Patent Document 1) discloses a semiconductor device used as a driver IC for driving in a flat panel display which can be implemented using a single-layer wiring board, the semiconductor device inhibiting an increase in impedance caused by long power supply wiring inside a flip chip associated with multi-pin outputs as well as a voltage drop at the longitudinally opposite ends of the inside of the flip chip, while enabling heat dissipation, power supply potential and system GND to be enhanced in spite of increased driving loads resulting from an increased size of a screen.
The semiconductor device described in the Patent Document 1 includes a semiconductor element on which an element electrode is provided, and a single-layer wiring board on which a board electrode electrically connected to the element electrode is provided. The semiconductor element is mounted on the single-layer wiring board. The semiconductor device is provided with a connector part, one or more radiator plates, a relay electrode part, and one or more connecting members. The connector part is provided at an end of the single-layer wiring board and receives an external signal including a first potential and a second potential for driving the semiconductor element. The radiator plate has electrical and thermal conductivity used for transmitting the first potential and/or the second potential. The relay electrode part is provided at one or a plurality of locations on the single-layer wiring board. The connecting member, which has electrical conductivity, is placed between the radiator plate and the relay electrode part to electrically connect the radiator plate and the relay electrode part together. The single-layer wiring board is structured so that the first potential and/or the second potential received by the connector part is transmitted to the element electrode of the semiconductor element through a path including the radiator plate, the relay electrode part, the connecting member and the board electrode.
The semiconductor device of the Patent Document 1 will be described referring to FIG. 3. FIG. 3 is a cross sectional view showing the configuration of the semiconductor device of the Patent Document 1. In FIG. 3, a semiconductor chip 100 is packaged in the TCP form. As shown in FIG. 3, a radiator plate 150 has a recess for mounting the semiconductor chip 100. The semiconductor chip 100 is placed in the recess on the radiator plate 150. Nonconductive thermal grease 160 being an insulating layer is applied to an interface between the radiator plate 150 and the semiconductor chip 100 to electrically isolate the semiconductor chip 100 and the radiator plate 150 from each other. The semiconductor chip 100 is provided with a high-voltage output part 101 and a low-voltage logic part. It should be noted that illustration of the low-voltage logic part is omitted in FIG. 3. The high-voltage output part 101 is connected to a VDD2 wiring 102 through a via to receive the power supply potential VDD2. Moreover, the high-voltage output part 101 is electrically connected to an inner lead (Lead Wire) 120 of the TCP through an output wiring 103, an output pad 104 and a bump 110. The high-voltage output part 101 outputs an output signal through the inner lead 120.
A terminal of the HVNch of the high-voltage output part 101 is connected to a VSS2 wiring 105 through a via. The VSS2 wiring 105 is connected to a VSS2 pad 106 through a via. A bump 111 is provided on the VSS2 pad 106 on a surface of the semiconductor chip 100. The bump 111 is connected to an inner lead 121 of the TCP. The inner lead 121 is formed on a base film 141 that is fixed to the radiator plate 150 by a double-faced tape 142. A surface of the inner lead 121 is covered with solder resist 140. A connecting member (screw) 130 penetrates the solder resist 140, the inner lead 121, the base film 141 and the double-faced tape 142 to be connected to the radiator plate 150. The connecting member 130 electrically connects the inner lead 121 and the radiator plate 150. The radiator plate 150 is connected to the system GND and is maintained at a predetermined potential. Thus, a predetermined potential is supplied to the high-voltage output part 101 through the VSS2 wiring 105, the VSS2 pad 106, the bump 111, the inner lead 121, the connecting member 130 and the radiator plate 150.
According to the semiconductor device of the Patent Document 1, the radiator plate 150 and the VSS2 pad 106 are electrically connected with each other through the connecting member 130, which can suppress high impedance due to a long wiring within the semiconductor chip 100. It is thus possible to enhance the system GND of the driver IC for driving.
The inventor of the present application has recognized the following points. In the case of the semiconductor device described in the Patent Document 1, the path from the VSS2 pad 106 of the semiconductor chip 100 to the system GND needs to pass through the bump 106, the inner lead 121, the connecting member 130 and the radiator plate 150. A resistance component of the wiring impedance increases with increase in the wiring length. Thus, in the case of the semiconductor device described in the Patent Document 1, the GND potential cannot be sufficiently stabilized when the drive load further increases due to increase in the size of the PDP panel. It is therefore required for the address driver IC to decrease the wiring impedance between the address driver IC and the system GND to further stabilize the GND potential.